\n", - " | 0 | \n", - "
---|---|
design | \n", - "/home/pierre/Bureau/freechips/semicustom/build | \n", - "
design_name | \n", - "xor3 | \n", - "
config | \n", - "RUN_2023.05.03_00.24.56 | \n", - "
flow_status | \n", - "flow completed | \n", - "
total_runtime | \n", - "0h0m18s0ms | \n", - "
routed_runtime | \n", - "0h0m9s0ms | \n", - "
(Cell/mm^2)/Core_Util | \n", - "7619.047619 | \n", - "
DIEAREA_mm^2 | \n", - "0.001575 | \n", - "
CellPer_mm^2 | \n", - "3809.52381 | \n", - "
OpenDP_Util | \n", - "7.16 | \n", - "
Final_Util | \n", - "-1 | \n", - "
Peak_Memory_Usage_MB | \n", - "468.28 | \n", - "
synth_cell_count | \n", - "2 | \n", - "
tritonRoute_violations | \n", - "0 | \n", - "
Short_violations | \n", - "0 | \n", - "
MetSpc_violations | \n", - "0 | \n", - "
OffGrid_violations | \n", - "0 | \n", - "
MinHole_violations | \n", - "0 | \n", - "
Other_violations | \n", - "0 | \n", - "
Magic_violations | \n", - "0 | \n", - "
pin_antenna_violations | \n", - "0 | \n", - "
net_antenna_violations | \n", - "0 | \n", - "
lvs_total_errors | \n", - "0 | \n", - "
cvc_total_errors | \n", - "-1 | \n", - "
klayout_violations | \n", - "-1 | \n", - "
wire_length | \n", - "127 | \n", - "
vias | \n", - "30 | \n", - "
wns | \n", - "0.0 | \n", - "
pl_wns | \n", - "-1 | \n", - "
optimized_wns | \n", - "-1 | \n", - "
fastroute_wns | \n", - "-1 | \n", - "
spef_wns | \n", - "0.0 | \n", - "
tns | \n", - "0.0 | \n", - "
pl_tns | \n", - "-1 | \n", - "
optimized_tns | \n", - "-1 | \n", - "
fastroute_tns | \n", - "-1 | \n", - "
spef_tns | \n", - "0.0 | \n", - "
HPWL | \n", - "138445.0 | \n", - "
routing_layer1_pct | \n", - "0.0 | \n", - "
routing_layer2_pct | \n", - "2.06 | \n", - "
routing_layer3_pct | \n", - "3.96 | \n", - "
routing_layer4_pct | \n", - "0.0 | \n", - "
routing_layer5_pct | \n", - "0.0 | \n", - "
routing_layer6_pct | \n", - "0.0 | \n", - "
wires_count | \n", - "5 | \n", - "
wire_bits | \n", - "5 | \n", - "
public_wires_count | \n", - "4 | \n", - "
public_wire_bits | \n", - "4 | \n", - "
memories_count | \n", - "0 | \n", - "
memory_bits | \n", - "0 | \n", - "
processes_count | \n", - "0 | \n", - "
cells_pre_abc | \n", - "2 | \n", - "
AND | \n", - "0 | \n", - "
DFF | \n", - "0 | \n", - "
NAND | \n", - "0 | \n", - "
NOR | \n", - "0 | \n", - "
OR | \n", - "0 | \n", - "
XOR | \n", - "2 | \n", - "
XNOR | \n", - "0 | \n", - "
MUX | \n", - "0 | \n", - "
inputs | \n", - "3 | \n", - "
outputs | \n", - "1 | \n", - "
level | \n", - "2 | \n", - "
DecapCells | \n", - "47 | \n", - "
WelltapCells | \n", - "5 | \n", - "
DiodeCells | \n", - "0 | \n", - "
FillCells | \n", - "9 | \n", - "
NonPhysCells | \n", - "6 | \n", - "
TotalCells | \n", - "67 | \n", - "
CoreArea_um^2 | \n", - "520.4992 | \n", - "
power_slowest_internal_uW | \n", - "-1 | \n", - "
power_slowest_switching_uW | \n", - "-1 | \n", - "
power_slowest_leakage_uW | \n", - "-1 | \n", - "
power_typical_internal_uW | \n", - "0.000001 | \n", - "
power_typical_switching_uW | \n", - "0.000002 | \n", - "
power_typical_leakage_uW | \n", - "0.0 | \n", - "
power_fastest_internal_uW | \n", - "-1 | \n", - "
power_fastest_switching_uW | \n", - "-1 | \n", - "
power_fastest_leakage_uW | \n", - "-1 | \n", - "
critical_path_ns | \n", - "0.67 | \n", - "
suggested_clock_period | \n", - "10.0 | \n", - "
suggested_clock_frequency | \n", - "100.0 | \n", - "
CLOCK_PERIOD | \n", - "10.0 | \n", - "
FP_ASPECT_RATIO | \n", - "1 | \n", - "
FP_CORE_UTIL | \n", - "50 | \n", - "
FP_PDN_HPITCH | \n", - "153.18 | \n", - "
FP_PDN_VPITCH | \n", - "153.6 | \n", - "
GRT_ADJUSTMENT | \n", - "0.3 | \n", - "
GRT_REPAIR_ANTENNAS | \n", - "1 | \n", - "
PL_TARGET_DENSITY | \n", - "0.6 | \n", - "
RUN_HEURISTIC_DIODE_INSERTION | \n", - "0 | \n", - "
STD_CELL_LIBRARY | \n", - "sky130_fd_sc_hd | \n", - "
SYNTH_MAX_FANOUT | \n", - "10 | \n", - "
SYNTH_STRATEGY | \n", - "AREA 0 | \n", - "