diff --git a/semicustom/semicustom.ipynb b/semicustom/semicustom.ipynb index b85b8d8..b4e9faa 100644 --- a/semicustom/semicustom.ipynb +++ b/semicustom/semicustom.ipynb @@ -100,19 +100,11 @@ }, { "cell_type": "code", - "execution_count": 1, + "execution_count": null, "metadata": { "id": "gpgkIYB739Ii" }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Writing v/xor3.v\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile v/xor3.v\n", "module xor3(\n", @@ -138,19 +130,11 @@ }, { "cell_type": "code", - "execution_count": 4, + "execution_count": null, "metadata": { "id": "rbT-vP0h0enK" }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Overwriting build/config.json\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile build/config.json\n", "{\n", @@ -177,7 +161,7 @@ }, { "cell_type": "code", - "execution_count": 5, + "execution_count": null, "metadata": { "colab": { "base_uri": "https://localhost:8080/" @@ -185,136 +169,7 @@ "id": "VP60fdObiP15", "outputId": "41aa85e4-c663-4778-d448-928dbe474b11" }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "env: PDK=sky130A\n", - "OpenLane 2023.04.07_0_gcb634fd5-conda\n", - "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.\n", - "Available under the Apache License, version 2.0. See the LICENSE file for more details.\n", - "\n", - "\u001b[36m[INFO]: Using configuration in 'build/config.json'...\u001b[39m\n", - "\u001b[36m[INFO]: PDK Root: /home/pierre/anaconda3/envs/semicustom/share/pdk\u001b[39m\n", - "\u001b[36m[INFO]: Process Design Kit: sky130A\u001b[39m\n", - "\u001b[36m[INFO]: Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", - "\u001b[36m[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", - "\u001b[33m[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.\u001b[39m\n", - "\u001b[36m[INFO]: DIODE_INSERTION_STRATEGY set to 3. Setting GRT_REPAIR_ANTENNAS to 1\u001b[39m\n", - "\u001b[36m[INFO]: Run Directory: /home/pierre/Bureau/freechips/semicustom/build/runs/RUN_2023.05.03_00.24.56\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the nom corner...\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the min corner...\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the max corner...\u001b[39m\n", - "[STEP 1]\n", - "\u001b[36m[INFO]: Running Synthesis (log: build/runs/RUN_2023.05.03_00.24.56/logs/synthesis/1-synthesis.log)...\u001b[39m\n", - "[STEP 2]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/synthesis/2-sta.log)...\u001b[39m\n", - "[STEP 3]\n", - "\u001b[36m[INFO]: Running Initial Floorplanning (log: build/runs/RUN_2023.05.03_00.24.56/logs/floorplan/3-initial_fp.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Floorplanned with width 23.92 and height 21.76.\u001b[39m\n", - "[STEP 4]\n", - "\u001b[36m[INFO]: Running IO Placement...\u001b[39m\n", - "[STEP 5]\n", - "\u001b[36m[INFO]: Running Tap/Decap Insertion (log: build/runs/RUN_2023.05.03_00.24.56/logs/floorplan/5-tap.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Power planning with power {VPWR} and ground {VGND}...\u001b[39m\n", - "[STEP 6]\n", - "\u001b[36m[INFO]: Generating PDN (log: build/runs/RUN_2023.05.03_00.24.56/logs/floorplan/6-pdn.log)...\u001b[39m\n", - "[STEP 7]\n", - "\u001b[36m[INFO]: Running Global Placement (log: build/runs/RUN_2023.05.03_00.24.56/logs/placement/7-global.log)...\u001b[39m\n", - "[STEP 8]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/placement/8-sta-global.log)...\u001b[39m\n", - "[STEP 9]\n", - "\u001b[36m[INFO]: Running Placement Resizer Design Optimizations (log: build/runs/RUN_2023.05.03_00.24.56/logs/placement/9-resizer.log)...\u001b[39m\n", - "[STEP 10]\n", - "\u001b[36m[INFO]: Running Detailed Placement (log: build/runs/RUN_2023.05.03_00.24.56/logs/placement/10-detailed.log)...\u001b[39m\n", - "[STEP 11]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/placement/11-sta.log)...\u001b[39m\n", - "[STEP 12]\n", - "\u001b[36m[INFO]: Running Placement Resizer Timing Optimizations (log: build/runs/RUN_2023.05.03_00.24.56/logs/cts/12-resizer.log)...\u001b[39m\n", - "[STEP 13]\n", - "\u001b[36m[INFO]: Running Global Routing Resizer Design Optimizations (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/13-resizer_design.log)...\u001b[39m\n", - "[STEP 14]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/14-sta-resizer_design.log)...\u001b[39m\n", - "[STEP 15]\n", - "\u001b[36m[INFO]: Running Global Routing Resizer Timing Optimizations (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/15-resizer_timing.log)...\u001b[39m\n", - "[STEP 16]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/16-sta-resizer_timing.log)...\u001b[39m\n", - "[STEP 17]\n", - "\u001b[36m[INFO]: Running Global Routing (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/17-global.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Starting OpenROAD Antenna Repair Iterations...\u001b[39m\n", - "[STEP 18]\n", - "\u001b[36m[INFO]: Writing Verilog (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/17-global_write_netlist.log)...\u001b[39m\n", - "[STEP 19]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/19-sta-groute.log)...\u001b[39m\n", - "[STEP 20]\n", - "\u001b[36m[INFO]: Running Fill Insertion (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/20-fill.log)...\u001b[39m\n", - "[STEP 21]\n", - "\u001b[36m[INFO]: Running Detailed Routing (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/21-detailed.log)...\u001b[39m\n", - "\u001b[36m[INFO]: No DRC violations after detailed routing.\u001b[39m\n", - "[STEP 22]\n", - "\u001b[36m[INFO]: Checking Wire Lengths (log: build/runs/RUN_2023.05.03_00.24.56/logs/routing/22-wire_lengths.log)...\u001b[39m\n", - "[STEP 23]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the min process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/23-parasitics_extraction.min.log)...\u001b[39m\n", - "[STEP 24]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/24-rcx_mcsta.min.log)...\u001b[39m\n", - "[STEP 25]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the max process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/25-parasitics_extraction.max.log)...\u001b[39m\n", - "[STEP 26]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/26-rcx_mcsta.max.log)...\u001b[39m\n", - "[STEP 27]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the nom process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/27-parasitics_extraction.nom.log)...\u001b[39m\n", - "[STEP 28]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/28-rcx_mcsta.nom.log)...\u001b[39m\n", - "[STEP 29]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/29-rcx_sta.log)...\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta\u001b[39m\n", - "[STEP 30]\n", - "\u001b[36m[INFO]: Creating IR Drop Report (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/30-irdrop.log)...\u001b[39m\n", - "[STEP 31]\n", - "\u001b[36m[INFO]: Running Magic to generate various views...\u001b[39m\n", - "\u001b[36m[INFO]: Streaming out GDSII with Magic (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/31-gdsii.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Generating MAGLEF views...\u001b[39m\n", - "[STEP 32]\n", - "\u001b[36m[INFO]: Streaming out GDSII with KLayout (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/32-gdsii-klayout.log)...\u001b[39m\n", - "[STEP 33]\n", - "\u001b[36m[INFO]: Running XOR on the layouts using KLayout (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/33-xor.log)...\u001b[39m\n", - "\u001b[36m[INFO]: No XOR differences between KLayout and Magic gds.\u001b[39m\n", - "[STEP 34]\n", - "\u001b[36m[INFO]: Running Magic Spice Export from LEF (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/34-spice.log)...\u001b[39m\n", - "[STEP 35]\n", - "\u001b[36m[INFO]: Writing Powered Verilog (logs: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/35-write_powered_def.log, build/runs/RUN_2023.05.03_00.24.56/logs/signoff/35-write_powered_verilog.log)...\u001b[39m\n", - "[STEP 36]\n", - "\u001b[36m[INFO]: Writing Verilog (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/35-write_powered_verilog.log)...\u001b[39m\n", - "[STEP 37]\n", - "\u001b[36m[INFO]: Running LVS (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/37-lvs.lef.log)...\u001b[39m\n", - "[STEP 38]\n", - "\u001b[36m[INFO]: Running Magic DRC (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/38-drc.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Converting Magic DRC database to various tool-readable formats...\u001b[39m\n", - "\u001b[36m[INFO]: No DRC violations after GDS streaming out.\u001b[39m\n", - "[STEP 39]\n", - "\u001b[36m[INFO]: Running OpenROAD Antenna Rule Checker (log: build/runs/RUN_2023.05.03_00.24.56/logs/signoff/39-antenna.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Saving current set of views in 'build/runs/RUN_2023.05.03_00.24.56/results/final'...\u001b[39m\n", - "\u001b[36m[INFO]: Saving runtime environment...\u001b[39m\n", - "\u001b[36m[INFO]: Generating final set of reports...\u001b[39m\n", - "\u001b[36m[INFO]: Created manufacturability report at 'build/runs/RUN_2023.05.03_00.24.56/reports/manufacturability.rpt'.\u001b[39m\n", - "\u001b[36m[INFO]: Created metrics report at 'build/runs/RUN_2023.05.03_00.24.56/reports/metrics.csv'.\u001b[39m\n", - "\u001b[36m[INFO]: There are no max slew, max fanout or max capacitance violations in the design at the typical corner.\u001b[39m\n", - "\u001b[36m[INFO]: There are no hold violations in the design at the typical corner.\u001b[39m\n", - "\u001b[36m[INFO]: There are no setup violations in the design at the typical corner.\u001b[39m\n", - "\u001b[32m[SUCCESS]: Flow complete.\u001b[39m\n", - "\u001b[36m[INFO]: Note that the following warnings have been generated:\u001b[39m\n", - "[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta\n", - "[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta\n", - "[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta\n", - "[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta\n", - "\n" - ] - } - ], + "outputs": [], "source": [ "%env PDK=sky130A\n", "!flow.tcl -design build" @@ -335,7 +190,7 @@ }, { "cell_type": "code", - "execution_count": 12, + "execution_count": null, "metadata": { "colab": { "base_uri": "https://localhost:8080/", @@ -345,3399 +200,7 @@ "outputId": "b4bd26f8-d3da-47b7-e321-99272b0591ef", "scrolled": false }, - "outputs": [ - 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power_typical_internal_uW0.000001
power_typical_switching_uW0.000002
power_typical_leakage_uW0.0
power_fastest_internal_uW-1
power_fastest_switching_uW-1
power_fastest_leakage_uW-1
critical_path_ns0.67
suggested_clock_period10.0
suggested_clock_frequency100.0
CLOCK_PERIOD10.0
FP_ASPECT_RATIO1
FP_CORE_UTIL50
FP_PDN_HPITCH153.18
FP_PDN_VPITCH153.6
GRT_ADJUSTMENT0.3
GRT_REPAIR_ANTENNAS1
PL_TARGET_DENSITY0.6
RUN_HEURISTIC_DIODE_INSERTION0
STD_CELL_LIBRARYsky130_fd_sc_hd
SYNTH_MAX_FANOUT10
SYNTH_STRATEGYAREA 0
\n", - "
" - ], - "text/plain": [ - " 0\n", - "design /home/pierre/Bureau/freechips/semicustom/build\n", - "design_name xor3\n", - "config RUN_2023.05.03_00.24.56\n", - "flow_status flow completed\n", - "total_runtime 0h0m18s0ms\n", - "routed_runtime 0h0m9s0ms\n", - "(Cell/mm^2)/Core_Util 7619.047619\n", - "DIEAREA_mm^2 0.001575\n", - "CellPer_mm^2 3809.52381\n", - "OpenDP_Util 7.16\n", - "Final_Util -1\n", - "Peak_Memory_Usage_MB 468.28\n", - "synth_cell_count 2\n", - "tritonRoute_violations 0\n", - "Short_violations 0\n", - "MetSpc_violations 0\n", - "OffGrid_violations 0\n", - "MinHole_violations 0\n", - "Other_violations 0\n", - "Magic_violations 0\n", - "pin_antenna_violations 0\n", - "net_antenna_violations 0\n", - "lvs_total_errors 0\n", - "cvc_total_errors -1\n", - "klayout_violations -1\n", - "wire_length 127\n", - "vias 30\n", - "wns 0.0\n", - "pl_wns -1\n", - "optimized_wns -1\n", - "fastroute_wns -1\n", - "spef_wns 0.0\n", - "tns 0.0\n", - "pl_tns -1\n", - "optimized_tns -1\n", - "fastroute_tns -1\n", - "spef_tns 0.0\n", - "HPWL 138445.0\n", - "routing_layer1_pct 0.0\n", - "routing_layer2_pct 2.06\n", - "routing_layer3_pct 3.96\n", - "routing_layer4_pct 0.0\n", - "routing_layer5_pct 0.0\n", - "routing_layer6_pct 0.0\n", - "wires_count 5\n", - "wire_bits 5\n", - "public_wires_count 4\n", - "public_wire_bits 4\n", - "memories_count 0\n", - "memory_bits 0\n", - "processes_count 0\n", - "cells_pre_abc 2\n", - "AND 0\n", - "DFF 0\n", - "NAND 0\n", - "NOR 0\n", - "OR 0\n", - "XOR 2\n", - "XNOR 0\n", - "MUX 0\n", - "inputs 3\n", - "outputs 1\n", - "level 2\n", - "DecapCells 47\n", - "WelltapCells 5\n", - "DiodeCells 0\n", - "FillCells 9\n", - "NonPhysCells 6\n", - "TotalCells 67\n", - "CoreArea_um^2 520.4992\n", - "power_slowest_internal_uW -1\n", - "power_slowest_switching_uW -1\n", - "power_slowest_leakage_uW -1\n", - "power_typical_internal_uW 0.000001\n", - "power_typical_switching_uW 0.000002\n", - "power_typical_leakage_uW 0.0\n", - "power_fastest_internal_uW -1\n", - "power_fastest_switching_uW -1\n", - "power_fastest_leakage_uW -1\n", - "critical_path_ns 0.67\n", - "suggested_clock_period 10.0\n", - "suggested_clock_frequency 100.0\n", - "CLOCK_PERIOD 10.0\n", - "FP_ASPECT_RATIO 1\n", - "FP_CORE_UTIL 50\n", - "FP_PDN_HPITCH 153.18\n", - "FP_PDN_VPITCH 153.6\n", - "GRT_ADJUSTMENT 0.3\n", - "GRT_REPAIR_ANTENNAS 1\n", - "PL_TARGET_DENSITY 0.6\n", - "RUN_HEURISTIC_DIODE_INSERTION 0\n", - "STD_CELL_LIBRARY sky130_fd_sc_hd\n", - "SYNTH_MAX_FANOUT 10\n", - "SYNTH_STRATEGY AREA 0" - ] - }, - "execution_count": 7, - "metadata": {}, - "output_type": "execute_result" - } - ], + "outputs": [], "source": [ "import glob\n", "import pandas as pd\n", @@ -4396,17 +351,9 @@ }, { "cell_type": "code", - "execution_count": 8, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Writing v/cnt.v\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile v/cnt.v\n", "module cnt(\n", @@ -4438,17 +385,9 @@ }, { "cell_type": "code", - "execution_count": 10, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Overwriting build/config.json\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile build/config.json\n", "{\n", @@ -4474,144 +413,11 @@ }, { "cell_type": "code", - "execution_count": 11, + "execution_count": null, "metadata": { "scrolled": true }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "env: PDK=sky130A\n", - "OpenLane 2023.04.07_0_gcb634fd5-conda\n", - "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.\n", - "Available under the Apache License, version 2.0. See the LICENSE file for more details.\n", - "\n", - "\u001b[36m[INFO]: Using configuration in 'build/config.json'...\u001b[39m\n", - "\u001b[36m[INFO]: PDK Root: /home/pierre/anaconda3/envs/semicustom/share/pdk\u001b[39m\n", - "\u001b[36m[INFO]: Process Design Kit: sky130A\u001b[39m\n", - "\u001b[36m[INFO]: Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", - "\u001b[36m[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", - "\u001b[33m[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.\u001b[39m\n", - "\u001b[36m[INFO]: DIODE_INSERTION_STRATEGY set to 3. Setting GRT_REPAIR_ANTENNAS to 1\u001b[39m\n", - "\u001b[36m[INFO]: Run Directory: /home/pierre/Bureau/freechips/semicustom/build/runs/RUN_2023.05.03_00.26.40\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the nom corner...\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the min corner...\u001b[39m\n", - "\u001b[36m[INFO]: Preparing LEF files for the max corner...\u001b[39m\n", - "[STEP 1]\n", - "\u001b[36m[INFO]: Running Synthesis (log: build/runs/RUN_2023.05.03_00.26.40/logs/synthesis/1-synthesis.log)...\u001b[39m\n", - "[STEP 2]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/synthesis/2-sta.log)...\u001b[39m\n", - "[STEP 3]\n", - "\u001b[36m[INFO]: Running Initial Floorplanning (log: build/runs/RUN_2023.05.03_00.26.40/logs/floorplan/3-initial_fp.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Floorplanned with width 28.52 and height 27.2.\u001b[39m\n", - "[STEP 4]\n", - "\u001b[36m[INFO]: Running IO Placement...\u001b[39m\n", - "[STEP 5]\n", - "\u001b[36m[INFO]: Running Tap/Decap Insertion (log: build/runs/RUN_2023.05.03_00.26.40/logs/floorplan/5-tap.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Power planning with power {VPWR} and ground {VGND}...\u001b[39m\n", - "[STEP 6]\n", - "\u001b[36m[INFO]: Generating PDN (log: build/runs/RUN_2023.05.03_00.26.40/logs/floorplan/6-pdn.log)...\u001b[39m\n", - "[STEP 7]\n", - "\u001b[36m[INFO]: Running Global Placement (log: build/runs/RUN_2023.05.03_00.26.40/logs/placement/7-global.log)...\u001b[39m\n", - "[STEP 8]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/placement/8-sta-global.log)...\u001b[39m\n", - "[STEP 9]\n", - "\u001b[36m[INFO]: Running Placement Resizer Design Optimizations (log: build/runs/RUN_2023.05.03_00.26.40/logs/placement/9-resizer.log)...\u001b[39m\n", - "[STEP 10]\n", - "\u001b[36m[INFO]: Running Detailed Placement (log: build/runs/RUN_2023.05.03_00.26.40/logs/placement/10-detailed.log)...\u001b[39m\n", - "[STEP 11]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/placement/11-sta.log)...\u001b[39m\n", - "[STEP 12]\n", - "\u001b[36m[INFO]: Running Clock Tree Synthesis (log: build/runs/RUN_2023.05.03_00.26.40/logs/cts/12-cts.log)...\u001b[39m\n", - "[STEP 13]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/cts/13-sta.log)...\u001b[39m\n", - "[STEP 14]\n", - "\u001b[36m[INFO]: Running Placement Resizer Timing Optimizations (log: build/runs/RUN_2023.05.03_00.26.40/logs/cts/14-resizer.log)...\u001b[39m\n", - "[STEP 15]\n", - "\u001b[36m[INFO]: Running Global Routing Resizer Design Optimizations (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/15-resizer_design.log)...\u001b[39m\n", - "[STEP 16]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/16-sta-resizer_design.log)...\u001b[39m\n", - "[STEP 17]\n", - "\u001b[36m[INFO]: Running Global Routing Resizer Timing Optimizations (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/17-resizer_timing.log)...\u001b[39m\n", - "[STEP 18]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/18-sta-resizer_timing.log)...\u001b[39m\n", - "[STEP 19]\n", - "\u001b[36m[INFO]: Running Global Routing (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/19-global.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Starting OpenROAD Antenna Repair Iterations...\u001b[39m\n", - "[STEP 20]\n", - "\u001b[36m[INFO]: Writing Verilog (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/19-global_write_netlist.log)...\u001b[39m\n", - "[STEP 21]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/21-sta-groute.log)...\u001b[39m\n", - "[STEP 22]\n", - "\u001b[36m[INFO]: Running Fill Insertion (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/22-fill.log)...\u001b[39m\n", - "[STEP 23]\n", - "\u001b[36m[INFO]: Running Detailed Routing (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/23-detailed.log)...\u001b[39m\n", - "\u001b[36m[INFO]: No DRC violations after detailed routing.\u001b[39m\n", - "[STEP 24]\n", - "\u001b[36m[INFO]: Checking Wire Lengths (log: build/runs/RUN_2023.05.03_00.26.40/logs/routing/24-wire_lengths.log)...\u001b[39m\n", - "[STEP 25]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the min process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/25-parasitics_extraction.min.log)...\u001b[39m\n", - "[STEP 26]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/26-rcx_mcsta.min.log)...\u001b[39m\n", - "[STEP 27]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the max process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/27-parasitics_extraction.max.log)...\u001b[39m\n", - "[STEP 28]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/28-rcx_mcsta.max.log)...\u001b[39m\n", - "[STEP 29]\n", - "\u001b[36m[INFO]: Running SPEF Extraction at the nom process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/29-parasitics_extraction.nom.log)...\u001b[39m\n", - "[STEP 30]\n", - "\u001b[36m[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/30-rcx_mcsta.nom.log)...\u001b[39m\n", - "[STEP 31]\n", - "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/31-rcx_sta.log)...\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta\u001b[39m\n", - "\u001b[33m[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta\u001b[39m\n", - "[STEP 32]\n", - "\u001b[36m[INFO]: Creating IR Drop Report (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/32-irdrop.log)...\u001b[39m\n", - "[STEP 33]\n", - "\u001b[36m[INFO]: Running Magic to generate various views...\u001b[39m\n", - "\u001b[36m[INFO]: Streaming out GDSII with Magic (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/33-gdsii.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Generating MAGLEF views...\u001b[39m\n", - "[STEP 34]\n", - "\u001b[36m[INFO]: Streaming out GDSII with KLayout (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/34-gdsii-klayout.log)...\u001b[39m\n", - "[STEP 35]\n", - "\u001b[36m[INFO]: Running XOR on the layouts using KLayout (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/35-xor.log)...\u001b[39m\n", - "\u001b[36m[INFO]: No XOR differences between KLayout and Magic gds.\u001b[39m\n", - "[STEP 36]\n", - "\u001b[36m[INFO]: Running Magic Spice Export from LEF (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/36-spice.log)...\u001b[39m\n", - "[STEP 37]\n", - "\u001b[36m[INFO]: Writing Powered Verilog (logs: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/37-write_powered_def.log, build/runs/RUN_2023.05.03_00.26.40/logs/signoff/37-write_powered_verilog.log)...\u001b[39m\n", - "[STEP 38]\n", - "\u001b[36m[INFO]: Writing Verilog (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/37-write_powered_verilog.log)...\u001b[39m\n", - "[STEP 39]\n", - "\u001b[36m[INFO]: Running LVS (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/39-lvs.lef.log)...\u001b[39m\n", - "[STEP 40]\n", - "\u001b[36m[INFO]: Running Magic DRC (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/40-drc.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Converting Magic DRC database to various tool-readable formats...\u001b[39m\n", - "\u001b[36m[INFO]: No DRC violations after GDS streaming out.\u001b[39m\n", - "[STEP 41]\n", - "\u001b[36m[INFO]: Running OpenROAD Antenna Rule Checker (log: build/runs/RUN_2023.05.03_00.26.40/logs/signoff/41-antenna.log)...\u001b[39m\n", - "\u001b[36m[INFO]: Saving current set of views in 'build/runs/RUN_2023.05.03_00.26.40/results/final'...\u001b[39m\n", - "\u001b[36m[INFO]: Saving runtime environment...\u001b[39m\n", - "\u001b[36m[INFO]: Generating final set of reports...\u001b[39m\n", - "\u001b[36m[INFO]: Created manufacturability report at 'build/runs/RUN_2023.05.03_00.26.40/reports/manufacturability.rpt'.\u001b[39m\n", - "\u001b[36m[INFO]: Created metrics report at 'build/runs/RUN_2023.05.03_00.26.40/reports/metrics.csv'.\u001b[39m\n", - "\u001b[36m[INFO]: There are no max slew, max fanout or max capacitance violations in the design at the typical corner.\u001b[39m\n", - "\u001b[36m[INFO]: There are no hold violations in the design at the typical corner.\u001b[39m\n", - "\u001b[36m[INFO]: There are no setup violations in the design at the typical corner.\u001b[39m\n", - "\u001b[32m[SUCCESS]: Flow complete.\u001b[39m\n", - "\u001b[36m[INFO]: Note that the following warnings have been generated:\u001b[39m\n", - "[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta\n", - "[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta\n", - "[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta\n", - "[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta\n", - "\n" - ] - } - ], + "outputs": [], "source": [ "%env PDK=sky130A\n", "!flow.tcl -design build" @@ -4637,17 +443,9 @@ }, { "cell_type": "code", - "execution_count": 13, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Writing xls/x/find_max.x\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile xls/x/find_max.x\n", "\n", @@ -4696,23 +494,11 @@ }, { "cell_type": "code", - "execution_count": 14, + "execution_count": null, "metadata": { "scrolled": true }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "[ RUN UNITTEST ] find_max_impl_test\n", - "[ OK ]\n", - "[ RUN UNITTEST ] find_max_test\n", - "[ OK ]\n", - "[===============] 2 test(s) ran; 0 failed; 0 skipped.\n" - ] - } - ], + "outputs": [], "source": [ "!interpreter_main xls/x/find_max.x" ] @@ -4726,39 +512,9 @@ }, { "cell_type": "code", - "execution_count": 15, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "module __find_max__find_max_impl(\r\n", - " input wire [127:0] array,\r\n", - " output wire [31:0] out\r\n", - ");\r\n", - " wire [31:0] array_unflattened[4];\r\n", - " assign array_unflattened[0] = array[31:0];\r\n", - " assign array_unflattened[1] = array[63:32];\r\n", - " assign array_unflattened[2] = array[95:64];\r\n", - " assign array_unflattened[3] = array[127:96];\r\n", - " wire [31:0] array_index_74;\r\n", - " wire [31:0] array_index_75;\r\n", - " wire [31:0] array_index_78;\r\n", - " wire [31:0] sel_79;\r\n", - " wire [31:0] array_index_82;\r\n", - " wire [31:0] sel_83;\r\n", - " assign array_index_74 = array_unflattened[2'h1];\r\n", - " assign array_index_75 = array_unflattened[2'h0];\r\n", - " assign array_index_78 = array_unflattened[2'h2];\r\n", - " assign sel_79 = array_index_74 > array_index_75 ? array_index_74 : array_index_75;\r\n", - " assign array_index_82 = array_unflattened[2'h3];\r\n", - " assign sel_83 = array_index_78 > sel_79 ? array_index_78 : sel_79;\r\n", - " assign out = array_index_82 > sel_83 ? array_index_82 : sel_83;\r\n", - "endmodule\r\n" - ] - } - ], + "outputs": [], "source": [ "XLS_DESIGN_NAME = 'find_max_impl'\n", "XLS_DESIGN_FILE = 'find_max'\n", @@ -4779,17 +535,9 @@ }, { "cell_type": "code", - "execution_count": 16, + "execution_count": null, "metadata": {}, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "Writing tb/xor3_tb.v\n" - ] - } - ], + "outputs": [], "source": [ "%%writefile tb/xor3_tb.v\n", "module xor3_tb;\n", @@ -4827,26 +575,11 @@ }, { "cell_type": "code", - "execution_count": 17, + "execution_count": null, "metadata": { "scrolled": true }, - "outputs": [ - { - "name": "stdout", - "output_type": "stream", - "text": [ - "VCD info: dumpfile tb/xor3_tb.vcd opened for output.\r\n", - "At time 0, value = 0 (0)\r\n", - "At time 5, value = 1 (1)\r\n", - "At time 15, value = 0 (0)\r\n", - "At time 20, value = 1 (1)\r\n", - "At time 25, value = 0 (0)\r\n", - "At time 35, value = 1 (1)\r\n", - "tb/xor3_tb.v:16: $finish called at 40 (1s)\r\n" - ] - } - ], + "outputs": [], "source": [ "!iverilog -o tb/xor3_tb tb/xor3_tb.v v/xor3.v\n", "!vvp tb/xor3_tb"