better hls example
* Add `find_max` hls example * Add gitignores * Make build cleaner * Add exercises in semicustom * Add food for brain in semicustom
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4 changed files with 183 additions and 43 deletions
2
fullcustom/.gitignore
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fullcustom/.gitignore
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.ipynb_checkpoints
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comp.out
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semicustom/.gitignore
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semicustom/.gitignore
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.ipynb_checkpoints
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semicustom/build/.gitignore
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semicustom/build/.gitignore
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*
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!.gitignore
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@ -136,21 +136,17 @@
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},
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"outputs": [],
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"source": [
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"%%writefile config.json\n",
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"%%writefile build/config.json\n",
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"{\n",
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" \"DESIGN_NAME\": \"xor3\",\n",
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" \"VERILOG_FILES\": \"dir::v/xor3.v\",\n",
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" \"VERILOG_FILES\": \"dir::../v/xor3.v\",\n",
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" \"CLOCK_TREE_SYNTH\": false,\n",
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" \"CLOCK_PORT\": null,\n",
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" \"PL_RANDOM_GLB_PLACEMENT\": true,\n",
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" \"FP_SIZING\": \"absolute\",\n",
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" \"DIE_AREA\": \"0 0 40 40\",\n",
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" \"PL_TARGET_DENSITY\": 0.8,\n",
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" \"DIE_AREA\": \"0 0 25 35\",\n",
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" \"FP_PDN_AUTO_ADJUST\": false,\n",
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" \"FP_PDN_VPITCH\": 10,\n",
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" \"FP_PDN_HPITCH\": 10,\n",
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" \"FP_PDN_VOFFSET\": 5,\n",
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" \"FP_PDN_HOFFSET\": 5,\n",
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" \"FP_PDN_VOFFSET\": 0,\n",
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" \"FP_PDN_HOFFSET\": 0,\n",
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" \"DIODE_INSERTION_STRATEGY\": 3\n",
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"}"
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]
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@ -176,7 +172,7 @@
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"outputs": [],
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"source": [
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"%env PDK=sky130A\n",
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"!flow.tcl -design ."
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"!flow.tcl -design build"
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]
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},
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{
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@ -210,7 +206,7 @@
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"import gdstk\n",
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"import IPython.display\n",
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"\n",
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"gdsii = sorted(glob.glob(\"./runs/*/results/final/gds/*.gds\"))[-1]\n",
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"gdsii = sorted(glob.glob(\"./build/runs/*/results/final/gds/*.gds\"))[-1]\n",
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"top = gdstk.read_gds(gdsii).top_level()\n",
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"top[0].write_svg('svg/inverter.svg')\n",
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"IPython.display.SVG('svg/inverter.svg')"
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@ -243,26 +239,15 @@
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},
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"id": "OWAwQI3fZC4W",
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"outputId": "d50dcf9f-30cd-42a3-dab5-12992bc9dca2",
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"scrolled": false
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"scrolled": true
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},
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"outputs": [],
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"source": [
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"import glob\n",
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"import pandas as pd\n",
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"pd.options.display.max_rows = None\n",
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"\n",
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"metrics = pd.read_csv(sorted(glob.glob(\"./runs/*/reports/metrics.csv\"))[-1])\n",
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"\n",
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"print(f\"tritonRoute_violations {metrics['tritonRoute_violations'][0]}\")\n",
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"print(f\"Short_violations {metrics['Short_violations'][0]}\")\n",
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"print(f\"OffGrid_violations {metrics['OffGrid_violations'][0]}\")\n",
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"print(f\"MinHole_violations {metrics['MinHole_violations'][0]}\")\n",
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"print(f\"Other_violations {metrics['Other_violations'][0]}\")\n",
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"print(f\"Magic_violations {metrics['Magic_violations'][0]}\")\n",
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"print(f\"pin_antenna_violations {metrics['pin_antenna_violations'][0]}\")\n",
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"print(f\"net_antenna_violations {metrics['net_antenna_violations'][0]}\")\n",
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"print(f\"lvs_total_errors {metrics['lvs_total_errors'][0]}\")\n",
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"print(f\"cvc_total_errors {metrics['cvc_total_errors'][0]}\")\n",
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"print(f\"klayout_violations {metrics['klayout_violations'][0]}\")"
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"pd.read_csv(sorted(glob.glob(\"./build/runs/*/reports/metrics.csv\"))[-1]).T"
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]
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},
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{
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@ -283,9 +268,22 @@
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"\n",
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"</summary>\n",
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"\n",
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"Nets which store data are declared as `reg`s:\n",
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" \n",
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"```verilog\n",
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"// Three scalar register\n",
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"reg op_b, op_a, result;\n",
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"// One 16-bit register\n",
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"reg [15:0] word_bus;\n",
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"// 1K-array of 8-bit registers\n",
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"reg [7:0] byte_array [0:1023];\n",
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"```\n",
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"\n",
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"The following structure updates the memory points:\n",
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" \n",
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"```verilog\n",
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"always @(posedge clk or negedge rst) begin\n",
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" if (rst) begin \n",
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" if (!rst) begin \n",
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" counter <= 0;\n",
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" end else begin\n",
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" counter <= counter + 1;\n",
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@ -347,7 +345,95 @@
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"```\n",
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"\n",
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"</details></blockquote>\n",
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" \n",
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"The counter example can be synthetized:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"%%writefile v/cnt.v\n",
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"module cnt(\n",
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" input wire clk,\n",
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" input wire rst,\n",
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" output wire [7:0] count\n",
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");\n",
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"\n",
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" reg [7:0] counter;\n",
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" assign count = counter;\n",
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"\n",
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" always @(posedge clk or negedge rst) begin\n",
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" if (!rst) begin \n",
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" counter <= 0;\n",
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" end else begin\n",
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" counter <= counter + 1;\n",
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" end\n",
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" end\n",
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"\n",
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"endmodule"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"For sequential circuits, one must specify to synthesize the clock tree as well:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"%%writefile build/config.json\n",
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"{\n",
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" \"DESIGN_NAME\": \"cnt\",\n",
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" \"VERILOG_FILES\": \"dir::v/cnt.v\",\n",
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" \"CLOCK_TREE_SYNTH\": true,\n",
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" \"CLOCK_PORT\": \"clk\",\n",
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" \"FP_SIZING\": \"absolute\",\n",
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" \"DIE_AREA\": \"0 0 40 50\",\n",
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" \"FP_PDN_AUTO_ADJUST\": false,\n",
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" \"FP_PDN_VOFFSET\": 0,\n",
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" \"FP_PDN_HOFFSET\": 0,\n",
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" \"DIODE_INSERTION_STRATEGY\": 3\n",
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"}"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The flow can be started:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"scrolled": true
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},
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"outputs": [],
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"source": [
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"%env PDK=sky130A\n",
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"!flow.tcl -design ."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The cell above can be reused to display the lyaout."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## High-Level Synthesis (HLS)\n",
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"\n",
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"RTL description of circuits does not follow an imperative programming paradigm. It is a description language that produces highly parallelized designs.\n",
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@ -361,18 +447,41 @@
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"metadata": {},
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"outputs": [],
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"source": [
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"%%writefile xls/x/adder.x\n",
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"pub fn adder(in1: u1, in2: u1) -> u2 {\n",
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" let sum: u2 = in1 as u2 + in2 as u2;\n",
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" sum\n",
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"%%writefile xls/x/find_max.x\n",
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"\n",
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"//\n",
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"// Input: an array of 32-bit unsigned integers (u32) of parametrized length N\n",
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"// Output: the largest element of the array\n",
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"//\n",
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"pub fn find_max<N: u32>(array: u32[N]) -> u32 {\n",
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" let max: u32 = u32:0;\n",
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" for (i, max): (u32, u32) in range(u32:0,N) {\n",
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" if (array[i] > max) {array[i]} else {max}\n",
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" }(max)\n",
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"}\n",
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"\n",
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"//\n",
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"// Input: an array of 32-bit unsigned integers (u32) of parametrized length 4\n",
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"// Output: the largest element of the array\n",
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"//\n",
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"pub fn find_max_impl(array: u32[4]) -> u32 {\n",
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" find_max<u32:4>(array)\n",
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"}\n",
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" \n",
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"#[test]\n",
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"fn find_max_impl_test() {\n",
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" let _= assert_eq(find_max_impl(u32[4]:[45,3,15,6]), u32:45);\n",
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" let _= assert_eq(find_max_impl(u32[4]:[3,45,15,6]), u32:45);\n",
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" let _= assert_eq(find_max_impl(u32[4]:[15,3,45,6]), u32:45);\n",
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" let _= assert_eq(find_max_impl(u32[4]:[6,3,15,45]), u32:45);\n",
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"}\n",
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"\n",
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"#[test]\n",
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"fn adder_test() {\n",
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" let _= assert_eq(adder(u1:0, u1:0), u2:0b00);\n",
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" let _= assert_eq(adder(u1:0, u1:1), u2:0b01);\n",
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" let _= assert_eq(adder(u1:1, u1:1), u2:0b10);\n",
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" _\n",
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"fn find_max_test() {\n",
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" let _= assert_eq(find_max<u32:1>(u32[1]:[39]), u32:39);\n",
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" let _= assert_eq(find_max<u32:2>(u32[2]:[4,90]), u32:90);\n",
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" let _= assert_eq(find_max<u32:3>(u32[3]:[7,21,15]), u32:21);\n",
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" let _= assert_eq(find_max<u32:8>(u32[8]:[1,3,45,1,5,56,0,34]), u32:56);\n",
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"}"
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]
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},
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},
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"outputs": [],
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"source": [
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"!interpreter_main xls/x/adder.x"
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"!interpreter_main xls/x/find_max.x"
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]
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},
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{
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"metadata": {},
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"outputs": [],
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"source": [
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"XLS_DESIGN_NAME = 'adder'\n",
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"!ir_converter_main --top={XLS_DESIGN_NAME} xls/x/{XLS_DESIGN_NAME}.x > xls/ir/{XLS_DESIGN_NAME}.ir\n",
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"!opt_main xls/ir/{XLS_DESIGN_NAME}.ir > xls/ir/{XLS_DESIGN_NAME}_opt.ir\n",
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"!codegen_main --generator=combinational xls/ir/{XLS_DESIGN_NAME}_opt.ir > v/{XLS_DESIGN_NAME}.v\n",
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"!cat v/{XLS_DESIGN_NAME}.v"
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"XLS_DESIGN_NAME = 'find_max_impl'\n",
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"XLS_DESIGN_FILE = 'find_max'\n",
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"!ir_converter_main --top={XLS_DESIGN_NAME} xls/x/{XLS_DESIGN_FILE}.x > xls/ir/{XLS_DESIGN_FILE}.ir\n",
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"!opt_main xls/ir/{XLS_DESIGN_FILE}.ir > xls/ir/{XLS_DESIGN_FILE}_opt.ir\n",
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"!codegen_main --generator=combinational xls/ir/{XLS_DESIGN_FILE}_opt.ir > v/{XLS_DESIGN_FILE}.v\n",
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"!cat v/{XLS_DESIGN_FILE}.v"
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]
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},
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{
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"source": [
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"## Verilog simulation\n",
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"\n",
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"A test bench can be written to simulate the circuit described above:"
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"A test bench can be written to simulate the `xor3` circuit described above:"
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]
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},
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{
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"metadata": {
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"scrolled": true
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},
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"outputs": [],
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"source": [
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"!iverilog -o tb/xor3_tb tb/xor3_tb.v v/xor3.v\n",
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"It can be opened with https://vc.drom.io/ for instance."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## Some ideas...\n",
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"\n",
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"Here are a couple ideas to spend a good time exploring those beautiful pieces of software:\n",
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"\n",
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" * Play with RTL2GDS configuration parameters and observe the impact on the layout.\n",
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" * Simulate the `cnt` sequential circuit.\n",
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" * Simulate the `find_max_impl` circuit synthesized using HLS.\n",
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" * Try to make _Klayout_ GUI work (no warranty).\n",
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"\n",
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" **Do not start from scratch! Use the provided examples, examples you can find on the internet and the documentation to adapt from them!**\n",
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" \n",
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" > Good luck and read the docs. 😉\n",
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" \n",
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"## More food for the brain\n",
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"\n",
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" * GDS2RTL flow configuration parameters: https://armleo-openlane.readthedocs.io/en/latest/docs/source/configuration.html\n",
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" * DSLX language reference: https://google.github.io/xls/dslx_reference/"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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