verilog reference + gitignores

semicustom/semicustom-inverter.ipynb

@@ -1,30 +1,101 @@
 {
  "cells": [
-  {
-   "cell_type": "markdown",
-   "metadata": {
-    "id": "HkFeU0R-0hzi"
-   },
-   "source": [
-    "# Semicustom digital design demo using OpenROAD"
-   ]
-  },
-  {
-   "cell_type": "markdown",
-   "metadata": {},
-   "source": [
-    "## Sources"
-   ]
-  },
   {
    "cell_type": "markdown",
    "metadata": {
     "id": "uINjDJNf39eD"
    },
    "source": [
+    "# Semicustom digital design demo using OpenROAD\n",
+    "\n",
+    "## Sources\n",
+    "\n",
     "### RTL description (Verilog)\n",
     "\n",
-    "The OpenROAD workflow takes the circuit's RTL description as an input. For instance, it can be a three bits XOR gate."
+    "The OpenROAD workflow takes the circuit's RTL description as an input. For instance, it can be a three bits XOR gate.\n",
+    "\n",
+    "\n",
+    "<blockquote><details>\n",
+    "\n",
+    "<summary>\n",
+    "    \n",
+    "#### ↕️ Types in Verilog\n",
+    "\n",
+    "</summary>\n",
+    "    \n",
+    "```verilog\n",
+    "// Three scalar nets\n",
+    "wire op_b, op_a, result;\n",
+    "// One 16-bit net\n",
+    "wire [15:0] word_bus;\n",
+    "// 1K-array of 8-bit nets\n",
+    "wire [7:0] byte_array [0:1023];\n",
+    "```\n",
+    "    \n",
+    "</details></blockquote>\n",
+    "\n",
+    "<blockquote><details>\n",
+    "\n",
+    "<summary>\n",
+    "    \n",
+    "#### ↕️ Assignation (non-blocking) in Verilog\n",
+    "\n",
+    "</summary>\n",
+    "    \n",
+    "```verilog\n",
+    "// 16-bit, hexadecimal constant\n",
+    "assign address = 16'hCAFE;\n",
+    "// Unsized, decimal constant\n",
+    "assign counter = 'd42;\n",
+    "// 1-bit, binary constant\n",
+    "assign answer = 1'b1;\n",
+    "\n",
+    "// Ternary assignation\n",
+    "assign muxed = which ? source_1 : source_2;\n",
+    "\n",
+    "// Concatenation\n",
+    "assign padded_packet = {5'b00000,body,suffix};\n",
+    "// Replication\n",
+    "assign odd_mask = {10{2'b10}};\n",
+    "\n",
+    "// Indexing\n",
+    "assign one_bit = bus[4];\n",
+    "assign bits = bus[15:12];\n",
+    "```\n",
+    "    \n",
+    "</details></blockquote>\n",
+    "\n",
+    "<blockquote><details>\n",
+    "\n",
+    "<summary>\n",
+    "    \n",
+    "#### ↕️ Operators in Verilog\n",
+    "\n",
+    "</summary>\n",
+    "    \n",
+    "```verilog\n",
+    "// Addition, substraction, negation\n",
+    "assign sum = op_a + op_b; assign sub = op_a + op_b; assign opp = -op_a\n",
+    "// Multiplication, division, modulo\n",
+    "assign prod = op_a * op_b; assign div = op_a / op_b; assign rem = op_a & op_b\n",
+    "    \n",
+    "// Bitwise not, or, and, xor\n",
+    "assign n = ~m; assign a = b | c; assign d = e & f; assign x = y ^ z\n",
+    "\n",
+    "// Logical not, and, or\n",
+    "assign ans = !v; assign ans = v || w; assign ans = v && w;\n",
+    "// Logical equality, difference\n",
+    "assign ans = v == w; assign ans = v != w;\n",
+    "// Relations (strictly) greater, (strictly) lower than\n",
+    "assign sg = a > b; assign gt = a >= b; assign sl = a < b; assign lt = a <= b;\n",
+    "    \n",
+    "// Left, right shift by n bits\n",
+    "assign l << n; assign r >> n;\n",
+    "// Left, right arithmetic shift by n bits\n",
+    "assign l <<< n; assign r >>> n;\n",
+    "```\n",
+    "    \n",
+    "</details></blockquote>"
    ]
   },
   {
@@ -35,8 +106,8 @@
    },
    "outputs": [],
    "source": [
-    "%%writefile v/inverter.v\n",
-    "module inverter(\n",
+    "%%writefile v/xor3.v\n",
+    "module xor3(\n",
     "    input wire a,\n",
     "    input wire b,\n",
     "    input wire c,\n",
@@ -67,8 +138,8 @@
    "source": [
     "%%writefile config.json\n",
     "{\n",
-    "    \"DESIGN_NAME\": \"inverter\",\n",
-    "    \"VERILOG_FILES\": \"dir::v/inverter.v\",\n",
+    "    \"DESIGN_NAME\": \"xor3\",\n",
+    "    \"VERILOG_FILES\": \"dir::v/xor3.v\",\n",
     "    \"CLOCK_TREE_SYNTH\": false,\n",
     "    \"CLOCK_PORT\": null,\n",
     "    \"PL_RANDOM_GLB_PLACEMENT\": true,\n",
@@ -108,19 +179,14 @@
     "!flow.tcl -design ."
    ]
   },
-  {
-   "cell_type": "markdown",
-   "metadata": {},
-   "source": [
-    "## Output products"
-   ]
-  },
   {
    "cell_type": "markdown",
    "metadata": {
     "id": "luguFgZ43AeL"
    },
    "source": [
+    "## Output products\n",
+    "\n",
     "### Display layout\n",
     "\n",
     "The implemented layout can be retrieved as follows:"
@@ -205,6 +271,83 @@
    "source": [
     "# To have fun going further...\n",
     "\n",
+    "## Sequential circuits in Verilog\n",
+    "\n",
+    "The tutorial above focuses on combinational circuits. Sequential circuits can obviously be described in Verilog as well. Sequential blocks feature an `always` block. Refer to the vendor's reference to get the sensitivity list's syntax (e.g. to determine if reset is synchronous or asynchronous).\n",
+    "\n",
+    "<blockquote><details>\n",
+    "\n",
+    "<summary>\n",
+    "    \n",
+    "#### ↕️ Sequential structures in Verilog\n",
+    "\n",
+    "</summary>\n",
+    "\n",
+    "```verilog\n",
+    "always @(posedge clk or negedge rst) begin\n",
+    "  if (rst) begin \n",
+    "    counter <= 0;\n",
+    "  end else begin\n",
+    "    counter <= counter + 1;\n",
+    "  end\n",
+    "end\n",
+    "```\n",
+    "    \n",
+    "</details></blockquote>\n",
+    "\n",
+    "Advanced structures like the `case` structure can be used to describe finite state machines. FSM decoders can be described in an abstract way using `always` blocks in a fully combinational way:\n",
+    "\n",
+    "<blockquote><details>\n",
+    "\n",
+    "<summary>\n",
+    "    \n",
+    "#### ↕️ Advanced structures in Verilog\n",
+    "\n",
+    "</summary>\n",
+    "\n",
+    "```verilog\n",
+    "    \n",
+    "/*\n",
+    " *   Case structure\n",
+    " */\n",
+    "    \n",
+    "case (state)\n",
+    "\n",
+    "  3'b000: idle_led <= 1'b1;\n",
+    "  \n",
+    "  3'b001,\n",
+    "  3'b010: work_led <= 1'b1;\n",
+    "  \n",
+    "  3'b011: begin\n",
+    "    muxed <= spi_1;\n",
+    "    work_led <= 1'b1;\n",
+    "  end\n",
+    "  \n",
+    "  default: begin\n",
+    "    muxed <= 0;\n",
+    "    work_led <= 1'b0; \n",
+    "    idle_led <= 1'b1;\n",
+    "  end\n",
+    "\n",
+    "endcase\n",
+    "\n",
+    "/*\n",
+    " *   Combinational always structure\n",
+    " *     To describe priorities in a procedural fashion,\n",
+    " *     use blocking `<=` assignations instead of\n",
+    " *     non-blocking `=` assignations.\n",
+    " */\n",
+    "                \n",
+    "always @( * ) begin\n",
+    "  flag <= 1'b0;\n",
+    "  if (error) begin \n",
+    "    flag <= 1'b1;\n",
+    "  end\n",
+    "end\n",
+    "```\n",
+    "\n",
+    "</details></blockquote>\n",
+    "\n",
     "## High-Level Synthesis (HLS)\n",
     "\n",
     "RTL description of circuits does not follow an imperative programming paradigm. It is a description language that produces highly parallelized designs.\n",
@@ -255,7 +398,7 @@
    "cell_type": "markdown",
    "metadata": {},
    "source": [
-    "Now that the imperative instructions are tested, the RTL design ca nby synthesized by _XLS_:"
+    "Now that the imperative instructions are tested, the RTL design can be synthesized by _XLS_:"
    ]
   },
   {

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+*.svg

semicustom/v/.gitignore

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+*.v

semicustom/xls/ir/.gitignore

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semicustom/xls/x/.gitignore

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