Pierre Guillod
4b8298e130
* Add Icarus Verilog exmple in semicustom * .gitignore files now ignore all files from the directory * add landsgemeinde
524 lines
14 KiB
Text
524 lines
14 KiB
Text
{
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"cells": [
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{
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"cell_type": "markdown",
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"metadata": {
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"id": "uINjDJNf39eD"
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},
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"source": [
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"# Semicustom digital design demo using OpenROAD\n",
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"\n",
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"## Sources\n",
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"\n",
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"### RTL description (Verilog)\n",
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"\n",
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"The OpenROAD workflow takes the circuit's RTL description as an input. For instance, it can be a three bits XOR gate.\n",
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"\n",
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"\n",
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"<blockquote><details>\n",
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"\n",
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"<summary>\n",
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" \n",
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"#### ↕️ Types in Verilog\n",
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"\n",
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"</summary>\n",
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" \n",
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"```verilog\n",
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"// Three scalar nets\n",
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"wire op_b, op_a, result;\n",
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"// One 16-bit net\n",
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"wire [15:0] word_bus;\n",
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"// 1K-array of 8-bit nets\n",
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"wire [7:0] byte_array [0:1023];\n",
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"```\n",
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" \n",
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"</details></blockquote>\n",
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"\n",
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"<blockquote><details>\n",
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"\n",
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"<summary>\n",
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" \n",
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"#### ↕️ Assignation (non-blocking) in Verilog\n",
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"\n",
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"</summary>\n",
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" \n",
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"```verilog\n",
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"// 16-bit, hexadecimal constant\n",
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"assign address = 16'hCAFE;\n",
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"// Unsized, decimal constant\n",
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"assign counter = 'd42;\n",
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"// 1-bit, binary constant\n",
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"assign answer = 1'b1;\n",
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"\n",
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"// Ternary assignation\n",
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"assign muxed = which ? source_1 : source_2;\n",
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"\n",
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"// Concatenation\n",
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"assign padded_packet = {5'b00000,body,suffix};\n",
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"// Replication\n",
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"assign odd_mask = {10{2'b10}};\n",
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"\n",
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"// Indexing\n",
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"assign one_bit = bus[4];\n",
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"assign bits = bus[15:12];\n",
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"```\n",
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" \n",
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"</details></blockquote>\n",
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"\n",
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"<blockquote><details>\n",
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"\n",
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"<summary>\n",
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" \n",
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"#### ↕️ Operators in Verilog\n",
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"\n",
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"</summary>\n",
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" \n",
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"```verilog\n",
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"// Addition, substraction, negation\n",
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"assign sum = op_a + op_b; assign sub = op_a + op_b; assign opp = -op_a\n",
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"// Multiplication, division, modulo\n",
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"assign prod = op_a * op_b; assign div = op_a / op_b; assign rem = op_a & op_b\n",
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" \n",
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"// Bitwise not, or, and, xor\n",
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"assign n = ~m; assign a = b | c; assign d = e & f; assign x = y ^ z\n",
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"\n",
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"// Logical not, and, or\n",
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"assign ans = !v; assign ans = v || w; assign ans = v && w;\n",
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"// Logical equality, difference\n",
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"assign ans = v == w; assign ans = v != w;\n",
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"// Relations (strictly) greater, (strictly) lower than\n",
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"assign sg = a > b; assign gt = a >= b; assign sl = a < b; assign lt = a <= b;\n",
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" \n",
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"// Left, right shift by n bits\n",
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"assign l << n; assign r >> n;\n",
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"// Left, right arithmetic shift by n bits\n",
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"assign l <<< n; assign r >>> n;\n",
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"```\n",
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" \n",
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"</details></blockquote>"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"id": "gpgkIYB739Ii"
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},
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"outputs": [],
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"source": [
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"%%writefile v/xor3.v\n",
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"module xor3(\n",
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" input wire a,\n",
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" input wire b,\n",
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" input wire c,\n",
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" output wire out\n",
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");\n",
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" assign out = a ^ b ^ c;\n",
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"endmodule"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {
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"id": "hp8h5vH8TUXr"
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},
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"source": [
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"### Configuration file (JSON)\n",
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"\n",
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"A configuration file should be provided. It describes constraints and strategies applied during synthesis and implementation of the circuit."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"id": "rbT-vP0h0enK"
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},
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"outputs": [],
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"source": [
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"%%writefile config.json\n",
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"{\n",
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" \"DESIGN_NAME\": \"xor3\",\n",
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" \"VERILOG_FILES\": \"dir::v/xor3.v\",\n",
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" \"CLOCK_TREE_SYNTH\": false,\n",
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" \"CLOCK_PORT\": null,\n",
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" \"PL_RANDOM_GLB_PLACEMENT\": true,\n",
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" \"FP_SIZING\": \"absolute\",\n",
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" \"DIE_AREA\": \"0 0 40 40\",\n",
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" \"PL_TARGET_DENSITY\": 0.8,\n",
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" \"FP_PDN_AUTO_ADJUST\": false,\n",
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" \"FP_PDN_VPITCH\": 10,\n",
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" \"FP_PDN_HPITCH\": 10,\n",
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" \"FP_PDN_VOFFSET\": 5,\n",
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" \"FP_PDN_HOFFSET\": 5,\n",
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" \"DIODE_INSERTION_STRATEGY\": 3\n",
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"}"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## Workflow\n",
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"The provided `flow.tcl` is a script describing the OpenROAD workflow. A _GDS_ file will be generated using the RTL circuit description, the PDK and the configuration file."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"colab": {
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"base_uri": "https://localhost:8080/"
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},
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"id": "VP60fdObiP15",
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"outputId": "41aa85e4-c663-4778-d448-928dbe474b11"
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},
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"outputs": [],
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"source": [
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"%env PDK=sky130A\n",
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"!flow.tcl -design ."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {
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"id": "luguFgZ43AeL"
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},
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"source": [
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"## Output products\n",
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"\n",
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"### Display layout\n",
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"\n",
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"The implemented layout can be retrieved as follows:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"colab": {
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"base_uri": "https://localhost:8080/",
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"height": 650
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},
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"id": "WOnhdtp3ivRi",
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"outputId": "b4bd26f8-d3da-47b7-e321-99272b0591ef",
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"scrolled": false
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},
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"outputs": [],
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"source": [
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"import glob\n",
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"import gdstk\n",
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"import IPython.display\n",
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"\n",
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"gdsii = sorted(glob.glob(\"./runs/*/results/final/gds/*.gds\"))[-1]\n",
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"top = gdstk.read_gds(gdsii).top_level()\n",
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"top[0].write_svg('svg/inverter.svg')\n",
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"IPython.display.SVG('svg/inverter.svg')"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {
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"id": "NW_7YdgTZYQK"
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},
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"source": [
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"### Reporting\n",
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"\n",
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"Many reports are available under:\n",
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"\n",
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"```\n",
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"freeechips/semicustom/runs/RUN_YYYY.MM.DD_HH.MM.SS/reports/.\n",
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"```\n",
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"\n",
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"An overview of the main figures can be retrieved as well:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"colab": {
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"base_uri": "https://localhost:8080/",
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"height": 1000
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},
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"id": "OWAwQI3fZC4W",
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"outputId": "d50dcf9f-30cd-42a3-dab5-12992bc9dca2",
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"scrolled": false
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},
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"outputs": [],
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"source": [
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"import glob\n",
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"import pandas as pd\n",
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"\n",
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"metrics = pd.read_csv(sorted(glob.glob(\"./runs/*/reports/metrics.csv\"))[-1])\n",
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"\n",
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"print(f\"tritonRoute_violations {metrics['tritonRoute_violations'][0]}\")\n",
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"print(f\"Short_violations {metrics['Short_violations'][0]}\")\n",
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"print(f\"OffGrid_violations {metrics['OffGrid_violations'][0]}\")\n",
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"print(f\"MinHole_violations {metrics['MinHole_violations'][0]}\")\n",
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"print(f\"Other_violations {metrics['Other_violations'][0]}\")\n",
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"print(f\"Magic_violations {metrics['Magic_violations'][0]}\")\n",
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"print(f\"pin_antenna_violations {metrics['pin_antenna_violations'][0]}\")\n",
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"print(f\"net_antenna_violations {metrics['net_antenna_violations'][0]}\")\n",
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"print(f\"lvs_total_errors {metrics['lvs_total_errors'][0]}\")\n",
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"print(f\"cvc_total_errors {metrics['cvc_total_errors'][0]}\")\n",
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"print(f\"klayout_violations {metrics['klayout_violations'][0]}\")"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"# To have fun going further...\n",
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"\n",
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"## Sequential circuits in Verilog\n",
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"\n",
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"The tutorial above focuses on combinational circuits. Sequential circuits can obviously be described in Verilog as well. Sequential blocks feature an `always` block. Refer to the vendor's reference to get the sensitivity list's syntax (e.g. to determine if reset is synchronous or asynchronous).\n",
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"\n",
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"<blockquote><details>\n",
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"\n",
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"<summary>\n",
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" \n",
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"#### ↕️ Sequential structures in Verilog\n",
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"\n",
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"</summary>\n",
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"\n",
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"```verilog\n",
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"always @(posedge clk or negedge rst) begin\n",
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" if (rst) begin \n",
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" counter <= 0;\n",
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" end else begin\n",
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" counter <= counter + 1;\n",
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" end\n",
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"end\n",
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"```\n",
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" \n",
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"</details></blockquote>\n",
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"\n",
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"Advanced structures like the `case` structure can be used to describe finite state machines. FSM decoders can be described in an abstract way using `always` blocks in a fully combinational way:\n",
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"\n",
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"<blockquote><details>\n",
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"\n",
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"<summary>\n",
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" \n",
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"#### ↕️ Advanced structures in Verilog\n",
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"\n",
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"</summary>\n",
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"\n",
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"```verilog\n",
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" \n",
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"/*\n",
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" * Case structure\n",
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" */\n",
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" \n",
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"case (state)\n",
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"\n",
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" 3'b000: idle_led <= 1'b1;\n",
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" \n",
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" 3'b001,\n",
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" 3'b010: work_led <= 1'b1;\n",
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" \n",
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" 3'b011: begin\n",
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" muxed <= spi_1;\n",
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" work_led <= 1'b1;\n",
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" end\n",
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" \n",
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" default: begin\n",
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" muxed <= 0;\n",
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" work_led <= 1'b0; \n",
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" idle_led <= 1'b1;\n",
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" end\n",
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"\n",
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"endcase\n",
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"\n",
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"/*\n",
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" * Combinational always structure\n",
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" * To describe priorities in a procedural fashion,\n",
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" * use blocking `<=` assignations instead of\n",
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" * non-blocking `=` assignations.\n",
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" */\n",
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" \n",
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"always @( * ) begin\n",
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" flag <= 1'b0;\n",
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" if (error) begin \n",
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" flag <= 1'b1;\n",
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" end\n",
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"end\n",
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"```\n",
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"\n",
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"</details></blockquote>\n",
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"\n",
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"## High-Level Synthesis (HLS)\n",
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"\n",
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"RTL description of circuits does not follow an imperative programming paradigm. It is a description language that produces highly parallelized designs.\n",
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"\n",
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"High-Level Synthesis provides an imperative language and a compiler that synthesizes the imperative instructions into RTL. For instance, _XLS_ provides a _Rust_-like language:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"%%writefile xls/x/adder.x\n",
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"pub fn adder(in1: u1, in2: u1) -> u2 {\n",
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" let sum: u2 = in1 as u2 + in2 as u2;\n",
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" sum\n",
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"}\n",
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"\n",
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"#[test]\n",
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"fn adder_test() {\n",
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" let _= assert_eq(adder(u1:0, u1:0), u2:0b00);\n",
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" let _= assert_eq(adder(u1:0, u1:1), u2:0b01);\n",
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" let _= assert_eq(adder(u1:1, u1:1), u2:0b10);\n",
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" _\n",
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"}"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Testing, parsing and linting can be performed prior to RTL synhesis:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"scrolled": true
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},
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"outputs": [],
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"source": [
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"!interpreter_main xls/x/adder.x"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Now that the imperative instructions are tested, the RTL design can be synthesized by _XLS_:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"XLS_DESIGN_NAME = 'adder'\n",
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"!ir_converter_main --top={XLS_DESIGN_NAME} xls/x/{XLS_DESIGN_NAME}.x > xls/ir/{XLS_DESIGN_NAME}.ir\n",
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"!opt_main xls/ir/{XLS_DESIGN_NAME}.ir > xls/ir/{XLS_DESIGN_NAME}_opt.ir\n",
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"!codegen_main --generator=combinational xls/ir/{XLS_DESIGN_NAME}_opt.ir > v/{XLS_DESIGN_NAME}.v\n",
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"!cat v/{XLS_DESIGN_NAME}.v"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## Verilog simulation\n",
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"\n",
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"A test bench can be written to simulate the circuit described above:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"%%writefile tb/xor3_tb.v\n",
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"module xor3_tb;\n",
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"\n",
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" wire value;\n",
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" reg w1, w2, w3;\n",
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" initial begin\n",
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" $dumpfile(\"tb/xor3_tb.vcd\");\n",
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" $dumpvars(0,xor3_tb);\n",
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" # 0 w1 = 0; w2 = 0; w3 = 0;\n",
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" # 5 w1 = 0; w2 = 0; w3 = 1;\n",
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" # 5 w1 = 0; w2 = 1; w3 = 0;\n",
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" # 5 w1 = 0; w2 = 1; w3 = 1;\n",
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" # 5 w1 = 1; w2 = 0; w3 = 0;\n",
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" # 5 w1 = 1; w2 = 0; w3 = 1;\n",
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" # 5 w1 = 1; w2 = 1; w3 = 0;\n",
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" # 5 w1 = 1; w2 = 1; w3 = 1;\n",
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" # 5 $finish;\n",
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" end\n",
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"\n",
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" xor3 xor3_i (w1, w2, w3, value);\n",
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"\n",
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" initial\n",
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" $monitor(\"At time %t, value = %h (%0d)\",\n",
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" $time, value, value);\n",
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"endmodule"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The simulation can then be performed using _Icarus Verilog_:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"!iverilog -o tb/xor3_tb tb/xor3_tb.v v/xor3.v\n",
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"!vvp tb/xor3_tb"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The waveforms are dumped in a `.vcd` file, located under:\n",
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"\n",
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|
"```\n",
|
|
"tb/xor3_tb.vcd\n",
|
|
"```\n",
|
|
"\n",
|
|
"It can be opened with https://vc.drom.io/ for instance."
|
|
]
|
|
},
|
|
{
|
|
"cell_type": "markdown",
|
|
"metadata": {},
|
|
"source": [
|
|
"# References\n",
|
|
"Inspired from:\n",
|
|
"“Silicon Notebooks.” CHIPS Alliance, Apr. 08, 2023. Accessed: Apr. 10, 2023. [Online]. Available: https://github.com/chipsalliance/silicon-notebooks/blob/b65134a43b01ae31423f7ee87110740b2257ac42/digital-inverter-openlane.ipynb (Apache License 2.0)"
|
|
]
|
|
}
|
|
],
|
|
"metadata": {
|
|
"colab": {
|
|
"name": "digital-inverter-openlane.ipynb",
|
|
"provenance": []
|
|
},
|
|
"kernelspec": {
|
|
"display_name": "Python 3 (ipykernel)",
|
|
"language": "python",
|
|
"name": "python3"
|
|
},
|
|
"language_info": {
|
|
"codemirror_mode": {
|
|
"name": "ipython",
|
|
"version": 3
|
|
},
|
|
"file_extension": ".py",
|
|
"mimetype": "text/x-python",
|
|
"name": "python",
|
|
"nbconvert_exporter": "python",
|
|
"pygments_lexer": "ipython3",
|
|
"version": "3.7.16"
|
|
}
|
|
},
|
|
"nbformat": 4,
|
|
"nbformat_minor": 1
|
|
}
|